1. Field of the Invention
The invention relates to a sine wave deflecting circuit, more particularly, to a sine wave deflecting circuit suitable for a CRT display.
2. Description of the Prior Art
A sine wave deflecting circuit using LC resonance, namely, what is called a bidirectional deflecting circuit is known. FIG. 1 shows an example of such a sine wave deflecting circuit. FIG. 2 shows waveform of a voltage VL0 which is generated across both ends of a deflecting yoke of the sine wave deflecting circuit, a current IL0 flowing in the deflecting yoke, and a pulse PEG, which will be explained hereinlater.
In a construction of FIG. 1, the power source voltage V+B is supplied to a pin distortion correcting circuit 76 through a terminal 75. In the pin distortion correcting circuit 76, a signal of a parabolic waveform of a vertical scanning period is formed. An output terminal of the pin distortion correcting circuit 76 is connected to a drain of an FET 78 through a coil 77.
A capacitor 79 and a damper diode 80 are connected in parallel with the drain of the FET 78. A capacitor 81 and a coil 82 which are connected in series are connected to the drain of the FET 78. The capacitor 81 is used to cut out a DC component. The coil 82 is used to smooth the signal. A gate terminal of the FET 78 is connected to a driving circuit 85. A source terminal of the FET 78 is connected to ground.
A driving section 71 is formed by the above FET 78, capacitor 79 and 81, coils 77 and 82, damper diode 80, driving circuit 85, and the like.
Capacitors 86 and 87 are serially connected to the other end side of the coil 82. The other end side of the capacitor 87 is connected to ground. A coil 88 as a deflecting yoke and a resistor 89 to detect the sine wave-shaped deflection current IL0 are serially connected to the other end side of the coil 82. The other end side of the resistor 89 is connected to ground. A capacitor 90 is connected to the other end side of the coil 82. The other end side of the capacitor 90 is connected to ground. The capacitor 90 constructs a parallel resonance circuit 95 together with the foregoing coil 88. Further, a switching circuit 93 comprising a diode 91 and an FET 92 is connected to the other end side of the coil 82.
In the switching circuit 93, an anode of the diode 91 is connected to the other end side of the coil 82. A cathode of the diode 91 is connected to a drain of the FET 92. A source of the FET 92 is connected to ground. A gate of the FET 92 is connected to an AFC control circuit 99.
The foregoing coil 88 and capacitor 90 perform the parallel resonance. The sine wave-shaped deflection current IL0 shown in FIG. 2B and generated by the resonance is used as a bidirectional current. The voltage VL0 shown in FIG. 2A and generated across both ends of the coil 88 is divided by the capacitors 86 and 87.
The voltage which is obtained from a middle point P3C between the coil 88 and the resistor 89 is supplied to the AFC control circuit 99. The voltage which is derived from a middle point P2C between the capacitors 86 and 87 is supplied to the AFC control circuit 99 and the driving circuit 85.
The AFC control circuit 99 controls the switching circuit 93 on the basis of the voltage obtained from the middle points P3C and P2C, thereby controlling a frequency (phase) so as not to change the amplitude of the deflection current IL0. In the driving circuit 85, when a predetermined time has passed after the voltage derived from the middle point P2C rises to a level higher than a predetermined threshold level, a control signal SCN10 to turn on the FET 78 is formed. The control signal SCN10 is supplied to the gate of the FET 78.
When the control signal SCN10 is supplied to the gate of the FET 78, the FET 78 is turned on and a signal which is generated from the pin distortion correcting circuit 76 flows to ground from the coil 77 and the drain of the FET 78 through the source thereof, so that the potential of the drain (at point P1 in FIG. 1) drops. Consequently, the potentials at points P2 and P3 on one end side of the capacitor 86 and coil 88 decrease and the potentials at the middle points P2C and P3C also drop. The potential at the middle point P2C is returned to the driving circuit 85.
The driving circuit 85 forms a control signal SCF10 to turn off the FET 78 when a predetermined time has passed after the potential at the middle point P2C is lower than a predetermined threshold level. The control signal SCF10 is supplied to the gate of the FET 78. When the control signal SCF10 is supplied to the gate of the FET 78, the FET 78 is turned off. When the FET 78 is turned off, the pulse PEG shown in FIG. 2C is formed by the operations of the capacitor 79, damper diode 80, and the like. The pulse PEG is supplied to the resonance circuit 95 as an energy to continue the resonance function. By repeating the above operations, the oscillation is continued.
The operation of the switching circuit 93 will now be described. The switching circuit 93 performs the AFC control by forming a rest interval, which will be explained hereinlater.
At an arbitrary timing after a time point t3 and before a time point t4 in FIGS. 2A and 2B, the AFC control circuit 99 forms a control signal SCN 20 to turn on the FET 92. The control signal SCN 20 is supplied to the gate of the FET 92. Time point t3 in FIGS. 2A and 2B is a time point when a state in which the deflection current IL0 is equal to 0 as detected as a voltage at the middle point P3C and a state in which the voltage VL0 is set to the maximum level on the negative side as detected at the middle point P2C. Time point t4 in FIGS. 2A and 2B is a time point when a state in which the voltage VL0 is equal to 0 is detected as a voltage at the middle point P2C and a state in which the defection current IL0 as set to the maximum level on the negative side is detected at the middle point P3C.
The FET 92 as turned on when the control signal SCN20 is supplied. On the other hand, the diode 91 is automatically turned on at a time point t4. Therefore, both ends of the coil 88 are short-circuited by the switching circuit 93. Thus, the energy accumulated in the coil 88 flows as a current IL0 along a path of the switching circuit 93, ground, resistor 89, and coil 88 and the energy is preserved.
At a time point t5, the AFC control circuit 99 forms a control signal SCF20 to turn off the FET 92. The control signal SCF20 is supplied to the gate of the FET 92. The FET 92 is turned off when the control signal SCF20 is supplied. Therefore, the switching circuit 93 is shut off and the path of the deflection current IL0 is shut off. As shown in FIGS. 2A and 2B, accordingly, a state of the voltage VL0 (=0) and the current IL0 (=the maximum level in the negative direction and the predetermined level) continues for a period of time between time points t4 and t5. That is, the period of time between t4 and t5 is the rest interval during which the resonance is stopped. By providing such a rest interval, an apparent resonance frequency can be changed and the AFC control can be performed.
For instance, in the waveform of the voltage VL0 shown in FIG. 2A, assuming that a period of time between t0 and t5 is set to one period, a period of time between t0 and t4 is a free resonance period of time and a period of time between t4 and t5 is a rest interval. Therefore, by controlling a duration of the rest interval and by maintaining the state in which all of the resonance energies in the rest interval are accumulated in the coil 88, the apparent resonance frequency can be changed and the AFC control can be performed.
There is a problem such that when the bidirectional deflection as mentioned above is executed, if a pure sine wave is used as a deflection current and the video signal is merely inverted every 1H, the image is extremely contracted at both edges of the screen on a CRT display.
A method of compressing the time base of the video signal is considered as one of countermeasures to prevent the image being extremely contracted at both edges of the screen as mentioned above. According to this method, by time-base compressing the video signal to about 80% of the ordinary signal, an overscan amount is adjusted so as to optimize the linearlity in accordance with the shape of each CRT, distance from the center of the deflection, and the like.
However, the time-base compression of the video signal denotes that the time during which the beam scans on the screen surface is reduced. Therefore, to set the brightness of the screen surface to a value similar to that of the ordinary television receiver, a beam current or a driving amount must be increased. However, there is a problem such that when the beam current or the driving amount is increased, a spot shape of beam is deteriorated and focusing characteristics are deteriorated or the life of the CRT is reduced. Since the horizontal scanning frequency rises by the time-base compression of the video signal, there is a problem such that the frequency characteristics of the signal processing system or the circuit to drive the CRT must be improved or the digital processing speed must be improved.
As another countermeasure, there is considered a method whereby a radius of curvature of the glass surface of the CRT screen is increased or a deflection angle is increased without time-base compressing the video signal. In this case, however, there is a problem such that the M-character characteristics of the linearity becomes remarkable and a good result cannot be obtained.
As still another countermeasure, a method of modulating the time base of the video signal along the linearity is also considered. However, in this case, there are problems such that not only the circuit becomes complicated but also drawbacks such as variation in luminance, variation in resolution, and the like occur.